3.1 Starting the Simulator

The simulation will be performed with the designated root module at the top-level. The simulator internally expands any module instances in your circuit. Since the path you take to get to a module is significant to the simulator, you cannot jump directly to submodules but must "navigate" your way to them by selecting a module at the current level and by opening it using the menu or the '>' keyboard command. You can leave a module you are in with the '<' keyboard command.

Gate and wire names in sub-modules are referenced by prepending a dot-separated "path" of module instance names. For instance, suppose there are two instances of a module named "foo" in the root module with instance names "g1" and "g2". Now suppose the "foo" module contains a wire named "w1". These wire names are referenced by the simulator as "g1.w1" and "g2.w1" to distinguish the two instances.

TkGate is an event-driven simulator. Time is measured in discrete units called "epochs". Each gate has a delay of a certain number of epochs. Some complex gates have multiple delay constants. In addition, some gates such as registers and memories have additional delay parameters which affect internal state changes.

The basic simulator commands are:

Function	Button	Description
Run		Enters continuous simulation mode. The simulation will continue as long as there are events in the event queue. If there are any clock gates in your circuit, this will mean the simulation will continue indefinately. If the circuit is combinational, the simulation will continue until the circuit reaches quiescence.
Pause		Causes a continuously running simulation to stop.
Step Epoch		Causes the simulation to advance a fixed number of epochs. The number of epochs to advance can be set on the simulation options menu. You can also invoke this command with the spacebar.
Step Cycle		Causes the simulation to advance to the rising edge of a clock. You can set the number of clock cycles to simulate and the number of epochs past the designated cycle to step (to allow time for registers to change value). The default is to trigger on any clock, but you can designate a specific clock in the simulator options menu. You can also invoke this command with the tab key.
End Simulation		Causes the simulation to be terminated and all probes to be deleted.

Other simulator commands will be discussed in the following sections.

3.2 Simulator Options

The simulator options are:

• Epoch Step Size: Specifies the number of epochs to step each time the simulator is stepped by using the step button or by pressing the space bar.
• Clock Cycle Step Size: Specifies the number of clock cycles to step each time the clock is stepped by using the clock step button or by pressing the tab key.
• Clock Overstep: Specifies the number of epochs to simulate past the clock edge when doing a clock step. This can be used to advance the simulator enough for registers to change value.
• Initialization Script: Specifies a simulation script to automatically execute when starting the simulator. The script file specified here is a global property and applys to any circuit that has been loaded into TkGate. To specify scripts specific to a particular circuit see circuit initalization scripts.
• Clock step stops on all clock posedges: Indicates that the clock step command should trigger on positive edges on all clocks in the circuit as.
• Clock step stops on clock: Indicates that the clock step command should trigger on positive edges only on the specified clock. This option is only useful for circuits with multiple clocks.
• Delay Files: Specifies additional files from which to load gate delay specifications. More on writting gate delay specifications can be found in Gate Delay Files

3.3 Observing the Output

Symbol	Scope	Description
0		Logic 0
1		Logic 1
x		Unknown
z		Floating
L		Low (the signal is either floating or zero)
H		High (the signal is either floating or one)

To display the value of a signal in a circuit, click and hold the mouse button on a wire. This will display the current value driven on the wire in verilog syntax. The value will disappear when you release the mouse button. This feature can be used both when the simulator is paused and when it is in continuous simulation mode. When the simulator is in continuous simulation mode, the value displayed will be the value at the time the mouse button was first pressed.

To set a permanent probe on a signal, double click on a wire. This will add or remove a probe. When a probe is set on a wire, its value will be continuously displayed in the scope window. The values of multi-bit signals will be displayed as hex numbers.

To change the range of values displayed and the scale of the display you can use the scrollbar, the mouse, or keyboard commands. Moving the scrollbar will set the range relative to the entire simulation run. You can get more fine grain control by clicking in the trace window with the left mouse button and dragging the trace left or right. To zoom in, you can either press the left mouse button while holding the shift key, or press the '>' key. To zoom out, you can either press the right mouse button while holding the shift key, or press the '<' key.

To print a scope trace, choose the "Print..." option from the "File" menu on the scope window, or use the keyboard shortcut "Ctl-s p". The dialog box shown here will be displayed. The left half of the dialog box is the same as the left half of the dialog box used to print circuits. The right half includes options for selecting the time range to print and the scale factor to use. Beware that simulation traces can grow very large, very quickly, especially when you use the continuous simulation mode. An estimate of the number of pages needed for each trace you have set is displayed to help you set parameters.

3.4 Controlling the Input

3.4.1 Switches and Dip Switches

3.4.2 Ttys

To send a character to a tty element, drive the RD input with the ascii code of the character to transmit and wait for the DTR output to go high. Next assert the DSR signal (positive high). The character will be transmitted on the positive edge of the DSR signal. You must then unassert the DSR signal so that the next character can be sent.

To receive a character, first unassert the CTS signal and wait for the RTS signal to go high. You can then read the value on the TD ouput of the tty. Once you have read the value, assert the CTS signal to indicate that you have received the character.

3.5 Setting Breakpoints

Button

Breakpoints can be used to set conditions which will cause a continuously running simulation to pause. To display the breakpoint dialog box, choose the "Breakpoint..." option from the "Simulate" menu. This will cause the breakpoint editor such as then one shown to the right to be displayed. You can use the button to add, edit or delete breakpoints.

When you add or edit a breakpoint, a breakpint editing dialog box such as the one shown here will be displayed. Enter or edit the breakpoint condition and hit OK. Currently, only a limited number of breakpoint types can be used. Only a single signal can be compared with a constant using a single relational operator. The relational operators are the standard relational operators used in C. The value must be a verilog syntax constant. Alternitively, you can simply type a signal name to break when the signal becomes non-zero, or a signal name prepended with the '!' operator to break when the signal becomes zero.

3.6 Initializing Memories

Function	Button	Description
Load Memory...		Load memories from the selected file. If a memory gate is selected, that memory will be the default memory to load. If the memory file contains one or more "memory" keywords, the specified memory(ies) will be loaded with the contents of the file. When loading a file, the current directory, the directory of the current circuit file, and the user's home directory will be searched.
Dump Memory...		Dumps the contents of the selected memory to a file.

100/ e1 f0 0 0 e1 e0 0 0
108/ 81 0 0 0 12 1 bd 0
110/ e 1 e1 d0 dc 7 85 0
118/ 6f 6 81 0 0 0 4e 4
120/ 69 f0 2 0 85 0 64 0
128/ 81 0 0 0 26 4 69 f0
130/ 2 0 ed 0 60 6 62 6
138/ ed 0 5e 6 1 0 85 0

If there is no "memory" keyword in the memory file, the selected memory gate will be loaded. The memory keyword requires a single argument specifing the name of a memory. For example:

memory memory.m1
100/ e1 f0 0 0 e1 e0 0 0
108/ 81 0 0 0 12 1 bd 0

For RAM memories, the contents of the loaded memory are frozen until first time the write line transitions to a stable value (logic 0 or 1). This prevents the data loaded from being destroyed due to unknown values on the write and address lines until the circuit has time to intitilize these signals.

3.7 Simulation Scripts

Button

You can also arrange for simulation scripts to be automatically executed when you start the simulator either by specifying a simulation script in the simulation options dialog box, or by adding simulation scripts as circuit options. The following simulation script commands are recognized. Arguments specified between "?" characters denote optional arguments.

3.8 Using the Error Reporter

3.9 Gate Delay Files

Each gate delay file should contain one or more technology blocks having the form:

technology cmos {
  ...
}

primitive mux {
  delay<I-Z> = (2*(num(S)+1) + 2*num(I)) + 2*(inv(I) || inv(Z)); 
  delay<S-Z> = (2*(num(S)+1) + 2*num(I));
  area = bits(Z)*((2*(num(S)+1) + 2*num(I)) + 2*inv(I)); 
}

Function	Description
num(p)	Normally, "p" specifies a group of related ports in which case this function returns the number of ports in the group. For example, on an n-input AND gate with inputs I1 through In, the expression num(I) would return n.
bits(p)	Returns the number of bits on the specified port. If "p" represents a group of ports, the highest bit-width of the group is returned.
inv(p)	When "p" is specific port, a 1 is returned if there is an inverter on the port, 0 otherwise. When "p" specifies a group of ports, the number of ports with inverters is returned.
log(expr)	Returns the ceiling of the base-2 log of an expression.

It is also possible to write procedural delay/area definitions. For example, consider the parameter specification for the "and" primitive.

primitive and {
  delay<I-Z> = {
    if ((inv(I) == num(I)))     // Determine if an inverter is necessary.  An
      d = inv(Z);               //   inverter is not required if the output is
    else if ((inv(I) == 0))     //   inverting and all inputs are non-inverting
      d = !inv(Z);              //   (i.e., it is an AND gate), or if all inputs
    else                        //   are inverting and the output is non-inverting
      d = 1;                    //   (i.e., it is a NOR gate). 

    if (num(I) == 1) {          // If one input, treat this as a reduction gate    
      return 2*bits(I0) + 2*d;  //   one Tr. delay per bit plus inverter delay.    
    } else {                    // If multiple inputs, treat this as a normal gate 
      return 2*num(I) + 2*d;    //   one Tr. delay per input plus inverter delay.  
    }
  }

  area = {
    if ((inv(I) == num(I)))     // Estimate number of inverters required.  If all
      d = inv(Z);               //   inputs are inverted, an inverter is required
    else if ((inv(I) == 0))     //   iff the output is inverted.  If all inputs
      d = !inv(Z);              //   are non-inverted, an inverter is required iff
    else                        //   the output is non-inverted.  Otherwise we need
      d = inv(I);               //   an inverter for each inverted input.

    if (num(I) == 1) {          // If one input, treat this as a reduction gate    
      a = 2*bits(I0) + 2*d;	//   one Tr. per bit plus inverter Trs.    
    } else {			// If multiple inputs, treat this as a normal gate 
      a = 2*num(I) + 2*d;	//   one Tr. per input plus inverter Trs.  
    }
    return bits(Z)*a;           // Multiply by number of bit slices.
  }
}

A technology block need not specify every single primitive type. For example, suppose we have a technology definition for CMOS which includes a definition for a buffer as shown here:

technology CMOS {
  primitive buf {
    delay<I-Z> = 2 + 2*(inv(I) == inv(Z));
    area = bits(Z)*(2 + 2*(inv(I) == inv(Z)));
  }
  ...rest of CMOS definition...
}

/*
 * A high-power buffer with half the delay and double the area/power.
 */
technology HP_CMOS {
  primitive buf {
    delay<I-Z> =  1 + (inv(I) == inv(Z));
    area = 2*bits(Z)*(2 + 2*(inv(I) == inv(Z)));
  }
}

If you assign the technology type HP_CMOS to any gates for which there is no primitive definition, delay values from the technology "default" will be used.

The table below lists all of the primitive gates for which delay may be specified and their delay parameters. The default values given are the values for a "basic" gate created from the "Make" with no changes to the number of inputs, input/output inverters, or bit widths of any of the ports.

3.10 Critical Path Analysis

To invoke the analyzer, click the critical path analysis button on the right side of the tool bar, or select "Critical Path..." from the "Circuit" menu. A dialog box like the one shown to the right with a list of top critical paths and their delays will appear. You can select a path to display by clicking on it in the listbox. The selected path will be shown in the edit window with red hashes as shown in the figure on the left.

The lower portion of the dialog box contains a list of the nets on the currently selected path. By clicking on a net name, the editor will go to the module with the selected net and highlight it with an "X" mark. The number of paths to by displayed can be selected with the selector in the lower right corner. Change this number and click on the "Recompute" button to change the number of displayed paths.

If you click on a net while in critical path analysis mode, a small window will appear next to the cursor with a message such as "10 -> w3 -> 50". This means that the selected net is "w3", the worst case delay from an input to w3 is 10, and the worst case delay from w3 to an output is 50.

To print a critial path, simply print the circuit while the path is highlighted.